 | Sun, Mon, and Wed 10:00-11:00 |
| Thu 11:00 - 12:00 |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 3rd ed., Morgan Kaufmann, 2005.
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Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 4th ed., Morgan Kaufmann, 2007.
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S. Palnitkar, Verilog HDL, 2nd Ed., Prentice Hall, 2003.
Using Verilog, the student designs and simulates the main parts of a computer: the ALU, registers, control unit, cache memory, system bus, and memory. At the end of the semester, the student integrates and simulates a complete computer design.
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| D. Hyde, Handbook on Verilog HDL, pdf. |
| Lib439.v |
| Experement I2: Introduction to Verilog - SR Latch |
| Experiment 1: Three-Port Register File |
| Experiment 2: 16-Bit ALU |
| Experiment 3: Five-Stage Pipeline Datapath - Arithmetic and Memory Instructions |
| Experiment 4: Five-Stage Pipeline Datapath - Adding Flow Control Instructions |
| Experiment 5: Five-Stage Pipeline Datapath - Solving Data Hazards |
| Experiment 6: Direct-Mapped Instruction Cache |