University of Jordan

Computer Engineering Department

CPE 231: Digital Logic

Fall 2009

 

Instructors Dr. Gheith Abandah, Dr. Ali Al-Haj, Dr. Walid Abu-Sufah, Eng. Mousa Al-Yaman
Email abandah@ju.edu.jo
Homepage http://www.abandah.com/gheith/Courses/CPE231_F09
Office Computer Engineering 405  
Office Hours for Dr. Abandah
bulletMon 10:00 - 11:00
bulletTue 10:00 - 11:00
bulletThu 12:00 - 1:00
  
Prerequisites 1900100 Computer Skills
Time and Room
bulletSection 1: Sun, Tue, and Thu 10:00-11:00, CPE 001 (Eng. Al-Yaman)
bulletSection 2: Sun, Tue, and Thu 11:00-12:00, CE 002 (Dr. Abandah)
bulletSection 3: Sun, Tue, and Thu 12:00-1:00, CE 002 (Dr. Abu-Sufah)
bulletSection 4: Mon and Wed 2:00-3:30, CE 102 (Dr. Abu-Sufah)
Textbook Logic and Computer Design Fundamentals, M. Morris Mano and Charles R. Kime (4th edition, 2008), Prentice Hall
Grading
Midterm Exam 30%
3 Homeworks and 2 tests: 3 marks for each homework, and 11 marks for the 2 tests. (Tentative) 20%
Final Exam 50%
   
Policies
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Attendance is required.

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All submitted work must be yours.

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Cheating will not be tolerated.

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Homeworks are due on exam or test dates
Tentative Outline
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Digital Systems and Numbering Systems

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Combinational Logic Circuits

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Combinational Logic Design

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Arithmetic Functions and HDLs

Midterm Exam

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Sequential Circuits

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Selected Design Topics

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Registers and Register Transfers

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Memory Basics

Final Exam

Special Dates
Sun 27 Sep 2009 Classes Begin
Sun 18 Oct 2009 Homework 1 Announcement
Sun 25 Oct 2009 Test 1 and Homework 1 Due
Sun 8 Nov 2009 Homework 2 Announcement
Thu 19 Nov 2009 Homework 2 is due in class.
Sat 21 Nov 2009 Midterm Exam (2:00-3:15 Tentative)
Sun 6 Dec 2009 Homework 3 Announcement
Sun 13 Dec 2009 Test 2 and Homework 3 Due
Thu 7 Jan 2010 Last Lecture
Mon 11 Jun 2010 Final Exam 2:00-4:00 pm (Tentative)
Handouts Course Syllabus

Slides

  1. Introduction
  2. Numbering Systems
  3. Combinational Logic Circuits - Part 1
  4. Combinational Logic Circuits - Part 2
  5. Combinational Logic Circuits - Part 3
  6. Combinational Logic Design - Part 1
  7. Combinational Logic Design - Part 2
  8. Arithmetic Functions
  9. Sequential Circuits - Part 1
  10. Sequential Circuits - Part 2
  11. Registers, Register Transfers, and Counters
  12. Programmable Implementation Technologies
  13. Memory Basics

Homeworks

  1. Homework 1: due in the class on Sun 25 Oct, 2009, Solution
  2. Homework 2: due Thu 19 Nov, 2009, Solution
  3. Homework 3: due in the class on Sun 13 Dec, 2009, Solution
  4. Homework 4

Quizzes and Exams

  1. Test 1 was given on Sun 25 Oct, 2009. Test Solution
  2. The Midterm exam was on Sat 21 Nov, 2009. Exam Solution
  3. Test 2 was given on Sun 13 Dec, 2009. Form A Solution, Form B Solution

 
Grades Section 2 grades as of 8/1/2010.