Course No: 22541
Course Name: Computer Architecture
Reading Assignment:
Chapter 1: Read Sections 1.4 through 1.11. Pay attention to: system CPU time, CPU time equation, CPI, instruction mix, wafer, die, yield, workload, benchmark, SPEC, geometric mean, Amdahl’s law, and MIPS (the metric). Also, examine the tables in Page 38, Figure 1.17, and Figure 1.22. Solve the “Check Yourself” problem in Page 38.
Chapter 2: The material in this chapter was covered in a previous course. Make sure that you know what is in Sections 2.1 through 2.10.
Chapter 4: Review Sections 4.1 through 4.5 that were covered in a previous course. Read Sections 4.6 through 4.14. Pay attention to: the five pipeline stages, pipeline control, forwarding and stalling, control hazards, reducing branch delay, dynamic branch prediction, BHT, BTB, exceptions and interrupts, vectored interrupts, instruction level parallelism, multiple issue, static scheduling, dynamic scheduling, speculation, VLIW, register renaming, reservation stations, commit unit, reorder buffer, out-of-order execution, AMD Opteron X4 pipeline.
Chapter 5: Read Sections 5.1 through 5.5, 5.7, 5.8, and 5.10. pay attention to: temporal and spatial localities, memory hierarchy, block, miss rate, hit time, miss penalty, direct-mapped cache, valid bit, tag, cache index, block offset, mapping an address to a cache block, effect of increasing the block size, write-through and write-back cashes, wide memory, interleaved memory, calculating memory stall cycles, AMAT, associative caches, replacement policies, multilevel caches, virtual memory, address translation, page tables, page faults, TLB, the common framework for memory hierarchy, cache miss categories, cache control using FSM, cache coherence, snooping protocols, and AMD Opteron X4 memory hierarchy.
Chapter 6: Read Sections 6.1 through 6.10.
Chapter 7: Read Sections 7.1 through 7.11.
Homeworks:
Homework 1: Due on the First Exam day on Wed 10/11/2010. Must be handwritten. Chapter 1: 3.4-5, 4.1-2, 4.4, 5.6, 7.1, 7.4, 8.1, 9.1-2, 10.1-3, 11.1-2, 12.1-3. Chapter 4: 19.1-3(a), 20.1-2(a), 20.4(a), 23.3(b), 24.1-3(a & b)
Homework 2: Due on the Second Exam day on Mon 27/12/2010. Must be handwritten. Follow the following link to download the (pdf) file.
Handouts:
Solutions:
- Solution of the First Exam (pdf)
- Solution of Homework 1 (doc) password protected
- Solution of the Second Exam (pdf)
Grades and Attendance:
- Grades and Attendance as of 5/1/2011 (pdf)
Last update on 12/1/2011, 12:18 pm.
Given a memory module made of Synchronous DRAM chips that run on a frequency of 400 MHz. If the module has 32-bit data bus and 50-ns access latency for the first word in the page mode operation, what is the time needed to access a four-word block?
in this question what is A page mode operation and when you say four-word block
does that mean direct mapped ?
and the time needed to access does that mean to eliminate the time for address transfer and data transfer?
This is SDRASM: you need one cycle to send the address, 50 ns latency, and 4 cycles to transfer the 4-word block.
Hi Dr. Gheith,
what is the textbook that you use to teach computer architecture
Regards
Dear Sedki,
I am using (Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 4th ed., Morgan Kaufmann, 2009) to teach Computer Archiecture in PSUT.
Regards,
-Gheith