University of Jordan

Computer Engineering Department

CPE 532: Performance Evaluation and Modeling

Spring 2006
Instructor Dr. Gheith Abandah
Email abandah@ju.edu.jo
Homepage http://www.abandah.com/gheith
Office Computer Engineering 405
Office Hours
bulletMonday 14:00-15:00
bulletSunday and Tuesday 10:00-11:00
Prerequisites Computer Design and Statistics
Time and Room Mon and Wed 12:30-14:00, CE 101
Textbook Raj Jain, The Art of Computer Systems Performance Analysis, Wiley, 1991.
References

  1. Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 3rd ed., Morgan Kaufmann, 2005.

  2. Hennessy, Patterson, and Goldberg. Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002.
Grading
Midterm Exam 30%
Second Exam 10%
Assignments 10%
Final Exam 50%
Policies
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Attendance is required

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All submitted work must be yours

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Cheating will not be tolerated
Tentative Outline
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Overview of Performance Evaluation

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Measurement Techniques and Tools

Midterm Exam

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Probability Theory and Statistics

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Experimental Design and Analysis

Second Exam

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Simulation

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Queuing Models

Final Exam
Handouts Homework 1 (due 13/3/2006)

Homework 2 (due 15/3/2006)

Assignment 3 (due 26/4/2006)

  A good reference for Verilog is Hyde's Handbook on Verilog HDL

  VeriLogger Pro from SynaptiCAD is a good Verilog simulation environment.

  Use the following library in your Verilog simulations: lib431.v

Assignment 4 (due 3/5/2006)

Assignment 5 (Due 15/5/2006) Assignment5.zip

Assignment 6 (due 29/5/2006)