University of Jordan

Electrical Engineering Department

EE 531

Computer Organization and Design

Fall 2000

 

Instructor Dr. Gheith Abandah
Email abandah@fet.ju.edu.jo
Home page http://fet.ju.edu.jo/abandah
Office EE 406
Office hours Sun, Tue 11-12, and Thu 9-10
No. of credit hrs 3
Prerequisites EE 331
Time and room Sun, Tue, and Thu 8:00-9:00, EE 002
Textbooks

  1. J. Hayes. Computer Architecture and Organization, 2nd ed., McGraw-Hill, 1998.
References

  1. Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann, 1995.

  2. H. Cragon. Memory Systems and Pipelined Processors, Jones and Partlett, 1996.

  3. K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, 1993.

  4. M. Mano. Computer System Architecture, 3rd ed., Prentice Hall, 1993.

  5. D. Hyde. Handbook on Verilog HDL. 80-KB pdf file.

  6. G. Blair. Verilog - Accelerating Digital Design. 24-KB pdf file.

  7. R. Madhavan. Quick Reference for Verilog HDL. 37-KB pdf file.

  8. Verilog Quick Reference Card. 37-KB pdf file.
Software Verilogger Pro - A Verilog Simulator (8.52 MB Zip file)
Grading Homework 10%
First Exam 20%
Second Exam 20%
Project 15%
Final Exam 35%
Tentative outline
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Introduction

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Design Methodology (Chapter 2)

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Verilog Hardware Description Language

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Basic Computer Organization and Design (Chapter 3)

First exam

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Datapath Design (Chapter 4)

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Control Design (Chapter 5)

Second exam

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Memory Organization (Chapter 6)

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Input/Output Organization (Chapter 7)

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Multiprocessors (Chapter 7)

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Future Trends

Final exam

Notes
Special dates
Important links http://www.syncad.com/ SynaptiCAD
Howeworks Homework 1: Use lib.v