 | Mon 10:00 - 11:00 |
| Tue 10:00 - 11:00 |
| Thu 12:00 - 1:00 |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 3rd ed., Morgan Kaufmann, 2005.
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Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 4th ed., Morgan Kaufmann, 2007.
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S. Palnitkar, Verilog HDL, 2nd Ed., Prentice Hall, 2003.
Using Verilog, the student designs and simulates the main parts of a computer: the ALU, registers, control unit, cache memory, system bus, and memory. At the end of the semester, the student integrates and simulates a complete computer design. The computer that will be built in this lab is based on the PIC 16F84A microcontroller (datasheet).
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| D. Hyde, Handbook on Verilog HDL, pdf. |
| Lib439.v |
| Experiment 1: Introduction to Verilog - SR Latch |
| Experiment 2: 8-bit Adder/Subtractor |
| Experiment 3: 8-bit ALU |
| Experiment 4: Datapath |
| Experiment 5: Program Memory |
| Experiment 6: Data Memory |
| Experiment 7: Data Memory - Part II |
| Experiment 8: The Processor Module |
| Experiment 9: The Control Module |
| Experiment 10: Full Processor Simulation |