 | Sunday 13:00-14:00 |
| Wednesday 14:00-15:00 |
| Thursday 10:00-11:00 |
| Section 1: Sun, Tue, and Thu 8:00-9:00, CE 002 |
| Section 2: Sun, Tue, and Thu 9:00-10:00, Middle Auditorium |
| Section 3: Mon and Wed 12:30-14:00, Mech 003 |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997.
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D. Culler and J.P. Singh with A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1998.
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J. Hayes. Computer Architecture and Organization, 3rd ed., McGraw-Hill, 1998.
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Introduction |
|
Instruction Set Principles |
|
Instruction-Level Parallelism and Its Dynamic Exploitation |
First exam
|
Exploiting Instruction-Level Parallelism with Software Approaches |
|
Memory Hierarchy Design |
Second exam
|
Multiprocessors and Thread-Level Parallelism |
|
Storage Systems |
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Interconnection Networks and Clusters |
Final exam
HW1:
Solve problems 1.3, 1.4, 1.9, and the following problem.
A program is executed on a 3-GHz processor. The program has the instruction counts shown in the table below. What is the CPU time?
| Instruction Type | Count | CPI |
| Memory | 1234 | 3 |
| Control | 2569 | 2 |
| ALU | 3912 | 1 |
HW2: 2.3, 2.4a, 2.6, 2.8, 2.11, 2.14, 2.18
HW3: A.1, A.2, A.3, A.4
HW4:
HW5: 4.1, 4.5, 4.7, 4.17, 4.20
Memory Technologies Presentation prepared by Sanad Bushnaq
Definition of Virtual Memory prepared by Ibrahim Sbieh
HW6: 5.1, 5.6, 5.16, 5.19