 | Sunday 13:00-14:00 |
| Tuesday 10:00-11:00 |
| Wednesday 14:00-15:00 |
| Section 1: Sun, Tue, and Thu 8:00-9:00, EE 002 |
| Section 2: Sun, Tue, and Thu 9:00-10:00, CE 002 |
| Section 3: Mon and Wed 12:30-14:00, Mech 003 |
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Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997.
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Hennessy, Patterson, and Goldberg. Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002.
|
Overview of Performance Evaluation |
|
Measurement Techniques and Tools |
First exam
|
Probability Theory and Statistics |
|
Experimental Design and Analysis |
Second exam
|
Simulation |
|
Queuing Models |
Final exam
A good reference for Verilog is Hyde's Handbook on Verilog HDL
VeriLogger Pro from SynaptiCAD is a good Verilog simulation environment.
Assignment 2 (Due December 2, 2004)
Use the following library in your Verilog simulations: lib431.v
Assignment 3 (Due December 30, 2004)
Assignment 4 (Due January 18, 2005) Assignment4.zip